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3 volt fast boot block flash memory 28f800f3 and 28f160f3 product features intel ? 3 volt fast boot block flash memory offers the highest performance synchronous burst readsmaking it an ideal memory solution for burst cpus. the intel 3 volt fast boot block flash memory also supports asynchronous page mode operation for non-clocked memory subsystems. combining high read performance with the intrinsic nonvolatility of flash memory eliminates the traditional redundant memory paradigm of shadowing code from a slower nonvolatile storage source to a faster execution memory device, (e.g., sram sdram), for improved system performance. by adding 3 volt fast boot block flash memory to your system you could reduce the total memory requirement, which helps increase reliability and reduce overall system power consumptionall while reducing system cost. this family of products is manufactured on intel ? 0.4 m m etox? v process technology. they are available in a wide variety of industry-standard packaging technologies. n high performance up to 60 mhz effective zero wait-state performance synchronous burst-mode reads asynchronous page-mode reads n smartvoltage technology 2.7 v - 3.6 v read and write operations for low power designs 12 v v pp fast factory programming n flexible i/o voltage 1.65 v i/o reduces overall system power consumption n 5 v-safe i/o enables interfacing to 5 v devices n enhanced data protection absolute write protection with v pp = gnd block locking block erase/program lockout during power transitions n density upgrade path 8 and 16 mbit n manufactured on etox? v flash technology n supports code plus data storage optimized for intel ? flash data integrator (ifdi) and other intel ? software fast program suspend capability fast erase suspend capability n flexible blocking architecture eight 4-kword blocks for data 32-kword main blocks for code top or bottom boot configurations n extended cycling capability minimum 100,000 block erase cycles n low power consumption automatic power savings mode decreases power consumption n automated program and block erase algorithms command user interface for automation status register for system feedback n industry-standard packaging 56-lead ssop 56-lead tsop m bga* csp intel ? easy bga order number: 290644-005 january 2000 notice: this document contains information on products in full production. the specifications are subject to change without notice. verify with your local intel sales office that you have the lat- est datasheet before finalizing a design.
information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such p roducts, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includ ing liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual p roperty right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 28f800f3 and 28f160f3 may contain design defects or errors known as errata which may cause the product to deviate from publ ished specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation 1998C2000 *other brands and names are the property of their respective owners.
iii 28f800f3 and 28f160f3 contents 1.0 introduction .................................................................................................................. 1 1.1 product overview .................................................................................................. 1 2.0 product description .................................................................................................. 2 2.1 pinouts .................................................................................................................. 2 2.2 pin description ...................................................................................................... 2 2.3 memory blocking organization ............................................................................. 7 2.3.1 parameter blocks ..................................................................................... 7 2.3.2 main blocks .............................................................................................. 7 3.0 principles of operation ..........................................................................................10 3.1 bus operations....................................................................................................10 3.1.1 read.......................................................................................................10 3.1.2 output disable........................................................................................10 3.1.3 standby ..................................................................................................11 3.1.4 write .......................................................................................................11 3.1.5 reset ......................................................................................................11 4.0 command definitions .............................................................................................12 4.1 read array command.........................................................................................13 4.2 read identifier codes command ........................................................................13 4.3 read status register command.........................................................................14 4.4 clear status register command.........................................................................14 4.5 block erase command........................................................................................14 4.6 program command .............................................................................................15 4.7 block erase suspend/resume command ..........................................................16 4.8 program suspend/resume command ...............................................................16 4.9 set read configuration command .....................................................................17 4.9.1 read configuration C (rcr.15) .............................................................18 4.9.2 frequency configuration code setting (fcc) C (rcr.13-11) ...............18 4.9.3 data output configuration C (rcr.9) ....................................................20 4.9.4 wait # configuration C (rcr.8)..............................................................21 4.9.5 burst sequence C (rcr.7).....................................................................21 4.9.6 clock configuration C (rcr.6) ...............................................................22 4.9.7 burst length C (rcr.20) ....................................................................22 4.9.8 continuous burst length........................................................................22 5.0 data protection .........................................................................................................27 5.1 v pp v pplk for complete protection..................................................................27 5.2 wp# = v il for block locking ...............................................................................27 5.3 wp# = v ih for block unlocking ...........................................................................27
28f800f3 and 28f160f3 iv 6.0 v pp voltages ............................................................................................................... 28 7.0 power consumption ............................................................................................... 28 7.1 active power ....................................................................................................... 28 7.2 automatic power savings ................................................................................... 28 7.3 standby power.................................................................................................... 28 7.4 power-up/down operation ................................................................................. 29 7.4.1 rst# connection................................................................................... 29 7.4.2 v cc , v pp and rst# transitions............................................................. 29 7.5 power supply decoupling ................................................................................... 29 7.5.1 v pp trace on printed circuit boards ...................................................... 30 8.0 electrical specifications ........................................................................................ 30 8.1 absolute maximum ratings ................................................................................ 30 8.2 extended temperature operating conditions..................................................... 31 8.3 capacitance ........................................................................................................ 31 8.4 dc characteristicsextended temperature...................................................... 32 8.5 ac characteristicsread-only operationsextended temperature............... 35 8.6 ac characteristicswrite operationsextended temperature ....................... 41 8.7 ac characteristicsreset operationextended temperature ........................ 43 8.8 extended temperature block erase and program performance........................ 44 9.0 ordering information .............................................................................................. 45 10.0 additional information ........................................................................................... 46
v 28f800f3 and 28f160f3 revision history date of revision version description 05/12/98 -001 original version 11/15/98 -002 minor text modifications revised page mode read waveform revised single synchronous read waveform improved automotive specifications changed name from fast boot block flash memory family 8 and 16 mbit . 03/22/99 -003 added easy bga pinout graphic added tsop and easy bga part number nomenclature 09/17/99 -004 minor text modifications revised figure 1, 8x8 easy bga package ballout revised section 4.9.2, frequency configuration added figure 7, data output with fcc setting at code 3 revised figure 12, block erase suspend/resume flowchart revised t elch , and t chqx specification added t ehel specification 01/12/2000 -005 corrected tsop pinout diagram corrected frequency configuration settings table added i cces and i ccws specifications increased t elch and t chqv

28f800f3 and 28f160f3 1 1.0 introduction this datasheet contains 8- and 16-mbit 3 volt intel ? fast boot block flash memory information. section 1.0 provides a flash memory overview. sections 2.0 through 8.0 describe the memory functionality and electrical specifications for extended temperature product offerings. 1.1 product overview the 3 volt fast boot block flash memory provides density upgrades with pinout compatibility for 8- and 16-mbit densities. this family of products is a high-performance, low-voltage memory with a 16-bit data bus and individually erasable blocks. these blocks are optimally-sized for code and data storage. eight 4-kword parameter blocks are positioned at either the top (denoted by -t suffix) or bottom (denoted by -b suffix) of the address map. the rest of the device is grouped into 32-kword main blocks. the upper two (or lower two) parameter blocks can be locked (wp# = v il ) for complete code protection. the devices optimized architecture and interface dramatically increase read performance beyond previously attainable levels. it supports synchronous burst reads and asynchronous page-mode reads from main blocks (parameter blocks support single synchronous and asynchronous reads). upon initial power-up or return from reset, the main blocks of the device default to a page-mode read configuration. page-mode read configuration is ideal for non-clocked memory systems and is compatible with page-mode rom. synchronous burst reads are enabled by configuring the read configuration register using the standard two-bus-cycle algorithm. in synchronous burst mode, the clk input increments an internal burst address generator, synchronizes the flash memory with the host cpu, and outputs data on every rising (or falling) clk edge up to 60 mhz. an output signal, wait#, is also provided to ease cpu-to-flash memory communication and synchronization during continuous burst operations that are not initiated on a four-word boundary. in addition to the enhanced architecture and optimized interface, this family of products incorporates smartvoltage technology which enables fast 12 volt factory programming and 2.7 vC 3.6 v in system programming for low power designs. specifically designed for low-voltage systems, 3 volt fast boot block flash memory components support read operations at 2.7 vC3.6 v (3.0 vC3.6 v for automotive temperature) v cc and block erase and program operations at 2.7 vC 3.6 v (3.0 vC3.6 v for automotive temperature) and 12 v v pp . the 12 v v pp option renders the fastest program performance to increase factory programming throughput. with the 2.7 v C3.6 v (3.0 vC3.6 v for automotive temperature) v pp option, v cc and v pp can be tied together for a simple, low power design. in addition to the voltage flexibility, the dedicated v pp pin gives complete data protection when v pp v pplk . the flexible input/output (i/o) voltage feature of the device helps reduce system power consumption and simplifies interfacing to sub 2.7 v cpus. powered by the v ccq pins, the i/o buffers can operate independently of the core voltage. the flexible i/o ring of the device works in three modes: 1. with v ccq voltage at 1.65 v, the i/os can swing between gnd and 1.65 v, reducing i/o power consumption by 65% over standard 3 v flash memory components. 2. with v cc and v ccq at 2.7 vC3.6v the device is an ideal fit for single supply voltage, low power, and battery-powered applications. 3. the 5 v-safe feature allows easy interface to 5 v i/o systems by tolerating 5 v cmos input levels. this helps ease cpu interfacing by adapting to cpus bus voltage without using buffers or level shifters.
28f800f3 and 28f160f3 2 the devices command user interface (cui) serves as the interface between the system processor and internal flash memory operation. a valid command sequence written to the cui initiates device automation. this automation is controlled by an internal write state machine (wsm) which automatically executes the algorithms and timings necessary for block erase and program operations. the status register provides wsm feedback by signifying block erase or program completion and status. block erase and program automation allows erase and program operations to be executed using an industry-standard two-write command sequence. a block erase operation erases one block at a time, and data is programmed in word (16 bit) increments. the erase suspend feature allows system software to suspend an ongoing block erase operation in order to read from or program data to any other block. the program suspend feature allows system software to suspend an ongoing program operation in order to read from any other location. the 3 volt fast boot block flash memory devices offer two low-power savings features: automatic power savings (aps) and standby mode. the device automatically enters aps mode following the completion of a read cycle. standby mode is initiated when the system deselects the device by driving ce# inactive or rst# active. rst# also resets the device to read array, provides write protection, and clears the status register. combined, these two features significantly reduce power consumption. 2.0 product description this section describes the pinout and block architecture of the device family. 2.1 pinouts intel 3 volt fast boot block flash memory provides upgrade paths in each package pinout up to the 16-mbit density. the family is available in easy bga, m bga csp, 56-lead ssop and 56-lead tsop packages. pinouts for the 8- and 16-mbit components are illustrated in figure 1 , figure 2 , figure 3 and figure 4 . 2.2 pin description the pin description table describes pin usage.
28f800f3 and 28f160f3 3 easypin01 notes: 1. a 20 is only valid on 32-mbit densities and above, a 21 is only valid on 64-mbit densities and above, a 22 is only valid on 128-mbit densities and above. all locations are populated with solder balls. 2. shaded connections on the top view indicate possible future upgrade address connections. 3. reference the preliminary mechanical specification for easy bga package at the intel? flash packaging data website, http://developer.intel.com/design/flash/packdata/index.htm, for detailed package specifications. figure 1. 8 x 8 easy bga package ballout 1 2 3 4 5 6 7 8 a b c d e f g h top view - ball side down bottom view - ball side up a 1 a 6 a 18 v pp v cc gnd a 10 a 15 a 2 a 17 a 19 rst# clk a 20 (1) a 11 a 14 a 3 a 7 wp# we# adv# a 21 (1) a 12 a 13 a 4 a 5 du dq 8 dq 1 dq 9 dq 3 dq 12 dq 6 du du ce# dq 0 dq 10 dq 11 dq 5 dq 14 du du a 0 v ssq dq 2 dq 4 dq 13 dq 15 gnd a 16 a 22 (1) oe# v ccq v cc v ssq dq 7 v ccq wait# du du du a 8 a 9 8 7 6 5 4 3 2 1 a b c d e f g h a 15 a 10 gnd v cc v pp a 18 a 6 a 1 a 14 a 11 a 20 (1) clk rst# a 19 a 17 a 2 a 13 a 12 a 21 (1) adv# we# wp# a 7 a 3 a 9 a 8 du du du dq 6 dq 12 dq 3 dq 9 dq 1 dq 8 du du dq 14 dq 5 dq 11 dq 10 dq 0 ce# a 16 gnd d 15 d 13 dq 4 dq 2 v ssq a 0 wait# v ccq d 7 v ssq v cc v ccq oe# a 22 (1) du du du a 5 a 4
28f800f3 and 28f160f3 4 notes: 1. shaded connections on the top view indicate upgrade address connections. lower density devices will not have upper address solder balls. routing is not recommended in this area. 2. a 20 and a 21 are the upgrade addresses for potential 32-mbit and 64-mbit devices. 3. reference the bga* package mechanical and shipping media specification at the intel? flash packaging data website, http://developer.intel.com/design/flash/packdata/index.htm, for detailed package specifications. figure 2. 56-ball bga* package ballout v pp v cc gnd clk a 15 a 14 a 11 we# adv# a 8 a 17 a 7 a 18 wp# a 9 a 10 a 13 v ccq dq 7 dq 13 dq 12 dq 4 dq 11 dq 10 dq 9 dq 1 dq 2 dq 3 v cc dq 5 dq 6 dq 15 a 16 a 12 87654321 dq 8 v ccq gnd dq 14 gnd wait# a b c d e f 9 10 a 4 a 1 a 5 a 2 a 3 a 6 dq 0 ce# a 0 oe# gnd rst# a 19 a 12 a 15 gnd clk v cc a 17 we# adv# a 8 a 11 a 14 a 13 a 10 a 9 wp# a 18 a 7 dq 9 dq 10 dq 11 dq 4 dq 12 dq 13 dq 7 v ccq a 16 dq 15 dq 6 dq 5 v cc dq 3 dq 2 dq 1 v pp 12345678 a b c d e pin #1 indicator wait# gnd dq 14 gnd v ccq dq 8 f a 4 a 5 a 6 dq 0 oe# 9 gnd a 1 a 2 a 3 ce# a 0 10 rst# a 19 top view, ball side down a 20 a 21 a 20 a 21 bottom view, ball side up
28f800f3 and 28f160f3 5 note: a 20 and a 21 are the upgrade addresses for potential 32-mbit and 64-mbit devices. note: a 20 and a 21 are the upgrade addresses for potential 32-mbit and 64-mbit devices. figure 3. ssop pinout 16-mbit we# we# rst# rst# v pp v pp wp# wp# nc a 19 a 1 a 1 a 2 a 2 a 3 a 3 a 4 a 4 a 5 a 5 a 6 a 6 a 7 a 7 a 17 a 17 a 18 a 18 dq 9 dq 9 dq 1 dq 1 dq 8 dq 8 dq 0 dq 0 oe# oe# gnd gnd ce# ce# a 0 a 0 nc nc v ccq v ccq dq 2 dq 2 dq 10 dq 10 dq 3 dq 3 dq 11 dq 11 v cc v cc clk clk adv# adv# gnd gnd nc nc a 15 a 15 a 14 a 14 a 13 a 13 a 12 a 12 a 11 a 11 a 10 a 10 a 9 a 9 a 8 a 8 nc nc gnd gnd dq 6 dq 6 dq 14 dq 14 dq 7 dq 7 dq 15 dq 15 gnd gnd v ccq v ccq a 16 a 16 wait# wait# dq 13 dq 13 dq 5 dq 5 dq 12 dq 12 dq 4 dq 4 v cc v cc 56-lead ssop 16 mm x 23.7 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 8-mbit 8-mbit 16-mbit --a 20 32-mbit --a 21 64-mbit figure 4. tsop pinout 56-lead tsop 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 wait# gnd dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 3 dq 10 dq 9 v ccq dq 2 dq 1 dq 0 oe# dq8 gnd nc ce# v cc dq 4 28f800f3 dq 11 v ccq a 16 8mbit 16mbit wait# gnd dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 3 dq 10 dq 9 v ccq dq 2 dq 1 dq 0 oe# dq 8 gnd nc ce# v cc dq 4 28f160f3 dq 11 v ccq a 16 16mbit 8mbit a 0 a 0 a 11 a 9 a 8 a 10 nc gnd adv# nc rst# wp# v cc clk 28f800f3 we# a 14 a 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 nc v pp a 12 a 13 a 11 a 9 a 8 a 10 nc gnd adv# nc rst# wp# v cc clk 28f800f3 we# a 14 a 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 v pp a 12 a 13 a 19 --a 21 64mbit --a 20 32mbit
28f800f3 and 28f160f3 6 table 1. pin descriptions sym type name and function a 0 C a 19 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during read and write cycles. 8-mbit: a 0C18 , 16-mbit: a 0C19 dq 0 C dq 15 input/ output data input/outputs: inputs data and commands during write cycles, outputs data during memory array, status register (dq 0 Cdq 7 ), and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. clk input clock: synchronizes the flash memory to the system operating frequency during synchronous burst mode read operations. when configured for synchronous burst-mode reads, the address is latched on the first rising (or falling, depending upon the read configuration register setting) clk edge when adv# is active or upon a rising adv# edge, whichever occurs first. clk is ignored during asynchronous page-mode read and write operations. adv# input address valid: indicates that a valid address is present on the address inputs. addresses are latched on the rising edge of adv# during read and write operations. adv# may be tied active during asynchronous read and write operations. ce# input chip enable: activates the devices control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. rst# input reset: when driven low, rst# inhibits write operations which provides data protection during power transitions, and it resets internal automation. rst#-high enables normal operation. exit from reset sets the device to asynchronous read array mode. oe# input output enable: gates data outputs during a read cycle. we# input write enable: controls writes to the cui and array. addresses and data are latched on the rising edge of the we# pulse. wp# input write protection: provides a method for locking and unlocking two parameter blocks. when wp# is at logic low, lockable blocks are locked. if a program or erase operation is attempted on a locked block, sr.1 and either sr.4 [program] or sr.5 [block erase] will be set to indicate the operation failed. when wp# is at logic high, the lockable blocks are unlocked and can be programmed or erased. wait# output wait: provides data valid feedback only when configured for synchronous burst mode and the burst length is set to continuous. this signal is gated by oe# and ce# and is internally pull-up to v ccq via a resistor. wait# from several components can be tied together to form one system wait# signal. v pp supply block erase and program power supply (2.7 vC3.6 v, 11.4 vC12.6 v): for erasing array blocks or programming data, a valid voltage must be applied to this pin. with v pp v pplk , memory contents cannot be altered. block erase and program with an invalid v pp voltage should not be attempted. applying 11.4 vC12.6 v to v pp can only be done for a maximum of 1000 cycles on main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum (see section 6.0 for details). v cc supply device power supply (2.7 vC3.6 v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltages should not be attempted. v ccq supply output power supply (1.65 vC2.5 v, 2.7 vC3.6 v): enables all outputs to be driven to 1.65 v to 2.5 v or 2.7 v to 3.6 v. when v ccq equals 1.65 vC2.5 v, v cc voltage must not exceed 3.3 v and should be regulated to 2.7 vC2.85 v to achieve lowest power operation (see dc characteristics for detailed information). for 5 v-tolerant operation v ccq must equal v cc voltage and must be regulated to 2.7 v to 3.6 v. this input may be tied directly to v cc . gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. (pins noted as possible upgrades to 32-mbit and 64-mbit densities can be connected to the appropriate address lines to pre- enable designs for possible future devices.).
28f800f3 and 28f160f3 7 2.3 memory blocking organization the 3 volt fast boot block flash memory family is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. for the address locations of each block, see the memory maps in figure 5, 8- and 16-mbit top boot memory map on page 8 (top boot blocking) and figure 6, 8- and 16-mbit bottom boot memory map on page 9 (bottom boot blocking). 2.3.1 parameter blocks the 3 volt fast boot block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally be stored in an eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. each 8- and 16-mbit device contains eight 4-kwords (4,096-words) parameter blocks. 2.3.2 main blocks after the parameter blocks, the remainder of the array is divided into equal size main blocks for code and/or data storage. the main blocks are the area of the device that support four-, eight-, and continuous burst operations. the 8-mbit device contains fifteen 32-kword (32,768-word) main blocks, and the 16-mbit device contains thirty-one 32-kword (32,768-word) main blocks.
28f800f3 and 28f160f3 8 0644_05 figure 5. 8- and 16-mbit top boot memory map 16-mbit 8-mbit 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 00000h - 07fffh 4-kword parameter block 19 4-kword parameter block 20 4-kword parameter block 21 4-kword parameter block 22 parameter blocks 4-kword parameter block 18 4-kword parameter block 17 4-kword parameter block 16 4-kword parameter block 15 7f000h - 7ffffh 7e000h -7efffh 7d000h - 7dfffh 7c000h - 7cfffh 7b000h - 7bfffh 7a000h - 7afffh 79000h - 79fffh 78000h - 78fffh eeprom replacement lockable blocks 32-kword main block 0 32-kword main block1 32-kword main block 2 32-kword main block 3 32-kword main block 4 32-kword main block 5 32-kword main block 6 32-kword main block 7 32-kword main block 8 32-kword main block 9 32-kword main block 10 32-kword main block 11 32-kword main block 12 32-kword main block 13 32-kword main block 14 main blocks burstable area 32-kword main block 0 32-kword main block 1 32-kword main block 2 32-kword main block 3 32-kword main block 4 32-kword main block 5 32-kword main block 6 32-kword main block 7 32-kword main block 8 32-kword main block 9 32-kword main block 10 32-kword main block 11 32-kword main block 12 32-kword main block 13 32-kword main block 14 32-kword main block 15 32-kword main block 16 32-kword main block 30 32-kword main block 17 32-kword main block 18 32-kword main block 19 32-kword main block 20 32-kword main block 21 32-kword main block 22 32-kword main block 23 32-kword main block 24 32-kword main block 25 32-kword main block 26 32-kword main block 27 32-kword main block 28 32-kword main block 29 main blocks burstable area f0000h - f7fffh e8000h - effffh e0000h - e7fffh d8000h - dffffh d0000h - d7fffh c8000h - cffffh c0000h - c7fffh b8000h - bffffh b0000h - b7fffh a8000h - affffh a0000h - a7fffh 98000h - 9ffffh 90000h - 97fffh 88000h - 8ffffh 80000h - 87fffh 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 08000h - 0ffffh 00000h - 07fffh 10000h - 17fffh 4-kword parameter block 35 4-kword parameter block 36 4-kword parameter block 37 4-kword parameter block 38 parameter blocks 4-kword parameter block 34 4-kword parameter block 33 4-kword parameter block 32 4-kword parameter block 31 eeprom replacement lockable blocks ff000h - fffffh fe000h - fefffh fd000h - fdfffh fc000h - fcfffh fb000h - fbfffh fa000h - fafffh f9000h - f9fffh f8000h - f8fffh address range address range
28f800f3 and 28f160f3 9 0644_06 figure 6. 8- and 16-mbit bottom boot memory map 16-mbit 8-mbit 07000h - 07fffh 06000h - 06fffh 05000h - 05fffh 04000h - 04fffh 03000h - 03fffh 02000h - 02fffh 01000h - 01fffh 00000h - 00fffh 32-kword main block 8 32-kword main block 9 32-kword main block 10 32-kword main block 11 32-kword main block 12 32-kword main block 13 32-kword main block 14 32-kword main block 15 32-kword main block 16 32-kword main block 17 32-kword main block 18 32-kword main block 19 32-kword main block 20 32-kword main block 21 32-kword main block 22 main blocks burstable area 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 32-kword main block 8 32-kword main block 9 32-kword main block 10 32-kword main block 11 32-kword main block 12 32-kword main block 13 32-kword main block 14 32-kword main block 15 32-kword main block 16 32-kword main block 17 32-kword main block 18 32-kword main block 19 32-kword main block 20 32-kword main block 21 32-kword main block 22 32-kword main block 23 32-kword main block 24 32-kword main block 38 32-kword main block 25 32-kword main block 26 32-kword main block 27 32-kword main block 28 32-kword main block 29 32-kword main block 30 32-kword main block 31 32-kword main block 32 32-kword main block 33 32-kword main block 34 32-kword main block 35 32-kword main block 36 32-kword main block 37 main blocks burstable area f8000h - fffffh f0000h - f7fffh e8000h - effffh e0000h - e7fffh d8000h - dffffh d0000h - d8fffh c8000h - cffffh c0000h - c7fffh b8000h - bffffh b0000h - b7fffh a8000h - affffh a0000h - a7fffh 98000h - affffh 90000h - 97fffh 88000h - 8ffffh 80000h - 87fffh 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 4-kword parameter block 4 4-kword parameter block 5 4-kword parameter block 6 4-kword parameter block 7 parameter blocks 4-kword parameter block 3 4-kword parameter block 2 4-kword parameter block 1 4-kword parameter block 0 eeprom replacement lockable blocks 4-kword parameter block 4 4-kword parameter block 5 4-kword parameter block 6 4-kword parameter block 7 parameter blocks 4-kword parameter block 3 4-kword parameter block 2 4-kword parameter block 1 4-kword parameter block 0 eeprom replacement lockable blocks 07000h - 07fffh 06000h - 06fffh 05000h - 05fffh 04000h - 04fffh 03000h - 03fffh 02000h - 02fffh 01000h - 01fffh 00000h - 00fffh address range address range
28f800f3 and 28f160f3 10 3.0 principles of operation the 3 volt fast boot block flash memory components include an on-chip write state machine (wsm) to manage block erase and program. it allows for cmos-level control inputs, fixed power supplies, and minimal processor overhead with ram-like interface timings. 3.1 bus operations the local cpu reads and writes flash memory in-system. all flash memory read and write cycles conform to standard microprocessor bus cycles. 3.1.1 read the flash memory has three read modes available: read array, identifier codes, and status register. these modes are accessible independent of the v pp voltage. the appropriate read command (read array, read identifier codes, or read status register) must be written to the cui to enter the requested read mode. upon initial power-up or exit from reset, the device defaults to read array mode. when reading information from main blocks in read array mode, the device supports two high- performance read configurations: synchronous burst mode and asynchronous page mode. page mode and synchronous burst-mode reads are enabled by writing the set read configuration register command to any device address. synchronous burst mode is enabled by writing to the read configuration register. this sets the read configuration, burst order, burst length, and frequency configuration. in synchronous burst mode, the device latches the initial address then outputs a sequence of data with respect to the input clk and read configuration setting. synchronous burst reads can be terminated after one cycle in main blocks. asynchronous page mode is the default state and provides a high data transfer rate for non- clocked memory subsystems. in this state, data is internally read and stored in a high-speed page buffer. a 1:0 addresses data in the page buffer. the page size is four words. read operations from the parameter blocks, identifier codes and status register transpire as single- synchronous or asynchronous read cycles. the read configuration register setting determines whether or not read operations are synchronous or asynchronous. for all read operations, ce# must be driven active to enable the devices, adv# must be driven low to open the internal address latch, and oe# must be driven low to activate the outputs. in asynchronous mode, the address is latched when adv# is driven high. in synchronous mode, the address is latched by adv# going high or adv# low in conjunction with a rising (falling) clock edge, whichever occurs first. we# must be at v ih . figure 17 through figure 22 illustrate the different read cycles. 3.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 15 are placed in a high-impedance state.
28f800f3 and 28f160f3 11 3.1.3 standby deselecting the device by bringing ce# to a logic-high level (v ih ) places the device in standby mode, which substantially reduces device power consumption. in standby, outputs are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 write commands are written to the cui using standard microprocessor write timings when adv#, we#, and ce# are active and oe# is inactive. the cui does not occupy an addressable memory location. the address is latched on the rising edge of adv#, we#, or ce# (whichever occurs first) and data needed to execute a command is latched on the rising edge of we# or ce# (whichever goes high first). write operations are asynchronous. therefore, clk is ignored during write operations. figure 23, ac waveform for write operations on page 42 illustrates a write operation. 3.1.5 reset the device enters a reset mode when rst# is driven low. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after return from reset, a time t phqv is required until outputs are valid, and a delay (t phwl or t phel ) is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the device defaults to read array mode, the status register is set to 80h, and the read configuration register defaults to asynchronous page-mode reads. if rst# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. see figure 24, ac waveform for reset operation on page 43 for detailed information regarding reset timings.
28f800f3 and 28f160f3 12 4.0 command definitions device operations are selected by writing specific commands into the cui. table 3 defines these commands. notes: 1. refer to dc characteristics . when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address input pins and v pplk or v pp1 or v pp2 for v pp . see dc characteristics for v pplk and v pp1 or v pp2 voltages. 3. command writes involving block erase or program are reliably executed when v pp = v pp1 or v pp2 and v cc = v cc1 or v cc2 (see section 8.0 for operating conditions at different temperatures). 4. refer to table 3 for valid d in during a write operation. notes: 1. commands other than those shown above are reserved by intel for future device implementations and should not be used. 2. bus operations are defined in table 2 . 3. x = any valid address within the device. ia = identifier code address. ba = address within the block being erased. wa = address of memory location to be written. rcd = data to be written to the read configuration register. this data is presented to the device on a 15-0 ; set all other address inputs to 0. see table 6, read configuration register definition on page 17 for a description of the read configuration register bits. table 2. bus operations mode notes rst# ce# adv# oe# we# address v pp dq 0C15 reset v il xxxxxxhigh z standby v ih v ih xxxxxhigh z output disable v ih v il xv ih v ih x x high z read 1,2 v ih v il v il v il v ih xxd out read identifier codes v ih v il v il v il v ih see table 4 x see table 4 write 3,4 v ih v il v il v ih v il xxd in table 3. command definitions (1) command bus cycles required notes first bus cycle second bus cycle oper (2) addr (3) data (4) oper (2) addr (3) data (4) read array/reset 1 write x ffh read identifier codes 3 2 5 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 6,7 write x 20h write ba d0h program 2 6,7,8 write x 40h or 10h write wa wd block erase and program suspend 1 6 write x b0h block erase and program resume 1 6 write x d0h set read configuration 2 write rcd 60h write rcd 03h
28f800f3 and 28f160f3 13 4. srd = data read from status register. see table 5, status register definition on page 15 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. see table 4 for manufacturer and device codes. 5. following the read identifier codes command, read operations access manufacturer, device codes, and read configuration register. 6. following a block erase, program, and suspend operation, read operations access the status register. 7. to issue a block erase, program, or suspend operation to a lockable block, hold wp# at v ih . 8. either 40h or 10h are recognized by the wsm as the program setup. 4.1 read array command upon initial device power-up or exit from reset, the device defaults to read array mode. the read configuration register defaults to asynchronous page mode. the read array command also causes the device to enter read array mode. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or program, the device will not recognize the read array command until the wsm completes its operation or unless the wsm is suspended via an erase or program suspend command. the read array command functions independently of the v pp voltage. 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. after writing the command, read cycles retrieve the manufacturer and device codes (see table 4 for identifier code values). page mode and burst reads are not supported in this read mode. to terminate the operation, write another valid command, like the read array command. the read identifier codes command functions independently of the v pp voltage. note: 1. read configuration register = rcd. table 4. identifier codes code address data manufacturer code 00000h 0089h device code 8 mbit -t 00001h 88f1h -b 00001h 88f2h 16 mbit -t 00001h 88f3h -b 00001h 88f4h read configuration register 00005h rcd (1)
28f800f3 and 28f160f3 14 4.3 read status register command the status register can be read at any time by writing the read status register command to the cui. after writing this command, all subsequent read operations output status register data until another valid command is written. page mode and burst reads are not supported in this read mode. the status register content is updated and latched on the rising edge of adv# or rising (falling) clk edge when adv# is low during synchronous burst mode or the falling edge of oe# or ce#, whichever occurs first. the read status register command functions independently of the v pp voltage. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be cleared by issuing the clear status register command. these bits indicate various error conditions. by allowing system software to reset these bits, several operations may be performed (such as cumulatively erasing or writing several bytes in sequence). the status register may be polled to determine if a problem occurred during the sequence. the clear status register command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is written first, followed by a block erase confirm. this command sequence requires appropriate sequencing and address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm. after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 10, automated block erase flowchart on page 23 ). the cpu can detect block erase completion by analyzing status register bit sr.7. when the block erase completes, check status register bit sr.5 for an error flag (1). if an error is detected, check status register bits sr.4, sr.3, and sr.1 to understand what caused the failure. after examining the status register, it should be cleared if an error was detected before issuing a new command. the device will remain in status register read mode until another command is written to the cui.
28f800f3 and 28f160f3 15 4.6 program command program operation is executed by a two-cycle command sequence. program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data. the wsm then takes over, controlling the internal program algorithm. after the program sequence is written, the device automatically outputs status register data when read (see figure 11, automated program flowchart on page 24 ). the cpu can detect the completion of the program event by analyzing status register bit sr.7. when the program operation completes, check status register bit sr.4 for an error flag (1). if an error is detected, check status register bits sr.5, sr.3, and sr.1 to understand what caused the problem. after examining the status register, it should be cleared if an error was detected before issuing a new command. the device will remain in status register read mode until another command is written to the cui. table 5. status register definition wsms ess es ps vpps pss dps r 76543210 notes: sr.7 = write state machine status (wsms) 1 = ready 0 = busy check sr.7 to determine block erase or program completion. sr.6C0 are invalid while sr.7 = 0. sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed when an erase suspend command is issued, the wsm halts execution and sets both sr.7 and sr.6 to 1. sr.6 remains set until an erase resume command is written to the cui. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase if both sr.5 and sr.4 are 1s after a block erase or program attempt, an improper command sequence was entered. sr.4 = program status (ps) 1 = error in program 0 = successful program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.3 does not provide a continuous v pp feedback. the wsm interrogates and indicates the v pp level only after a block erase or program operation. sr.3 is not guaranteed to report accurate feedback when v pp 1 v pph1 or v pph2 or v pplk . sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when a program suspend command is issued, the wsm halts execution and sets both sr.7 and sr.2 to 1. sr.2 remains set until a program resume command is written to the cui. sr.1 = device protect status (dps) 1 = block erase or program attempted on a locked block, operation abort 0 = unlocked if a block erase or program operation is attempted on a locked block, sr.1 is set by the wsm and aborts the operation if wp# = v il . sr.0 = reserved for future enhancements (r) sr.0 is reserved for future use and should be masked out when polling the status register.
28f800f3 and 28f160f3 16 4.7 block erase suspend/resume command the block erase suspend command allows block erase interruption to read or program data in another block. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase operation after a certain latency period. the device continues to output status register data when read after the block erase suspend command is issued. status register bits sr.7 and sr.6 indicate when the block erase operation has been suspended (both will be set to 1). specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. using the program suspend command (see section 4.8 ), a program operation can be suspended during an erase suspend. the only other valid commands while block erase is suspended are read status register and block erase resume. during a block erase suspend, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pp1 or v pp2 while block erase is suspended. wp# must also remain at v il or v ih . to resume the block erase operation, write the block erase resume command to the cui. this will automatically clear status register bits sr.6 and sr.7. after the erase resume command is written, the device automatically outputs status register data when read (see figure 12, block erase suspend/resume flowchart on page 25 ). block erase cannot resume until program operations initiated during block erase suspend have completed. 4.8 program suspend/resume command the program suspend command allows program interruption to read data in other flash memory locations. once the program process starts, writing the program suspend command requests that the wsm suspend the program operation after a certain latency period. the device continues to output status register data when read after issuing the program suspend command. status register bits sr.7 and sr.2 indicate when the program operation has been suspended (both will be set to 1). specification t whrh1 defines the program suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. the only other valid commands while program is suspended are read status register and program resume. during a program suspend, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pp1 or v pp2 while program is suspended. wp# must also remain at v il or v ih . to resume the program, write the program resume command to the cui. this will automatically clear status register bits sr.7 and sr.2. after the program resume command is written, the device automatically outputs status register data when read (see figure 13, program suspend/resume flowchart on page 26 ).
28f800f3 and 28f160f3 17 4.9 set read configuration command the set read configuration command writes data to the read configuration register. this operation is initiated by a standard two bus cycle command sequence. the read configuration setup command (60h) is written and the data to be written to the read configuration is presented, which is then followed by a second write that confirms the operation and again presents the data to be written to the read configuration register. the read configuration register data is placed on the address bus, a 15:0 ,during both bus cycles and is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). the read configuration register data sets the devices read configuration, burst order, frequency configuration, burst length and all other parameters. this command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. table 6. read configuration register definition rm r fc2 fc1 fc0 r doc wc 15 14 13 12 11 10 9 8 bs cc r r r bl2 bl1 bl0 76543210 notes: rcr.15 = read mode (rm) 0 = synchronous burst reads enabled 1 = page mode reads enabled (default) read mode configuration affects reads from main blocks. parameter block, status register, and identifier reads support single read cycles. rcr.14 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0. rcr.13C11 = frequency configuration (fc2-0) 001 = code 1 reserved for future use 010 = code 2 011 = code 3 100 = code 4 101 = code 5 110 = code 6 see section 4.9.2 for information about the frequency configuration and its effect on the initial read. undocumented combinations of bits rcr.14C11 are reserved by intel corporation for future implementations and should not be used. rcr.10 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0. rcr.9 = data output configuration (doc) 0 = hold data for one clock 1 = hold data for two clocks undocumented combinations of bits rcr.10C9 are reserved by intel corporation for future implementations and should not be used. rcr.8 = wait configuration (wc) 0 = wait# asserted during delay 1 = wait# asserted one data cycle before delay rcr.7 = burst sequence (bs) 0 = intel burst order 1 = linear burst order rcr.6 = clock configuration (cc) 0 = burst starts and data output on falling clock edge 1 = burst starts and data output on rising clock edge rcr.5C3 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0. rcr.2C0 = burst length (bl2C0) 001 = 4 word burst 010 = 8 word burst 111 = continuous burst in the asynchronous page mode, the burst length always equals four words. undocumented combinations of bits rcr.2C0 are reserved by intel corporation for future implementations and should not be used
28f800f3 and 28f160f3 18 4.9.1 read configuration C (rcr.15) the device supports two high performance read configurations: synchronous burst mode and asynchronous page mode. bit rcr.15 in the read configuration register sets the read configuration to either synchronous burst or asynchronous page mode. asynchronous page mode is the default read configuration state. parameter blocks, status register, and identifier modes only support single-synchronous and asynchronous read operations. 4.9.2 frequency configuration code setting (fcc) C (rcr.13-11) the frequency configuration code setting informs the device of the number of clocks that must elapse after adv# is driven active before data will be available. this value is determined by the input clock frequency and the set up and hold requirements of the target system. see table 7, frequency configuration settings on page 20 for the specific input clk frequency configuration codes. the frequency configuration codes in table 7 are derived from equations (1), (2) and (3) with assumed values for the t avqv, t add, t data parameters. below is the example of the calculation to obtain the frequency configuration code: flash performance can be determined by the following equations: {1/frequency (mhz)}1000 = clk period (ns) (1) n(clk period) 3 t av q v (ns) + t add (ns) + t data (ns) (2) n-2 = frequency configuration code (fcc) * (3) n : # of clock periods (rounded up to the next integer) * must use fcc = n - 1 when operating in the continous burst mode. parameters defined by cpu : t add = clock to ce#, adv#, or address valid whichever occurs last. t data = data set up to clock parameters defined by flash : t avqv = address to output delay example : cpu clock speed = 50 mhz t add = 6 ns (typical speed from cpu) (max) t data = 4 ns (typical speed from cpu) (min) t avqv = 90 ns (from section 8.5 ac characteristic - read only operations table) from eq. (1): {1/50 (mhz)}1000 = 20 ns from eq. (2) n(20 ns) 3 90 ns + 6 ns + 4 ns n(20 ns) 3 100 ns n 3 100/20 3 5 (integer) from eq. (3) n - 2 = 5 - 2 = 3 frequency code setting to the rcr is code 3 the formula t avqv (ns) + t add (ns) + t data (ns) is also known as initial access time.
28f800f3 and 28f160f3 19 note: 1. figure 7 shows the data output available and valid after 4 latencies from adv# going low in the 1st clock period with the fcc setting at 3. figure 8 illustrates data output latency from adv# going active for different frequency configuration codes. figure 7. data output with fcc setting at code 3 a 15-0 valid address dq 15-0 (d/q) clk (c) ce# adv# r13 valid output valid output high z t add t data 2nd 1st 3rd 4th 5th figure 8. frequency configuration adv# (v) a 19-0 (a) valid address clk (c) dq 15-0 (d/q) valid output dq 15-0 (d/q) valid output valid output valid output valid output dq 15-0 (d/q) valid output valid output valid output valid output dq 15-0 (d/q) valid output valid output dq 15-0 (d/q) valid output valid output valid output valid output code 2 code 3 code 4 code 5 code 6
28f800f3 and 28f160f3 20 note: table derived by using formulas (1), (2) and (3) in section 4.9.2 . values of t add , t data defined by cpu, assumed to be 6 ns and 4 ns respectively; value of t avqv per section 8.5 . 4.9.3 data output configuration C (rcr.9) the output configuration determines the number of clocks during which data will be held valid. the data hold time is configurable as either one or two clocks. subsequent reads in burst mode with zero wait-states can be defined by: t chqv (ns) + t data (ns) one clk period (4) in table 7 , consider the cpu clock at 50 mhz, and fcc is 3. the clock period is 20 ns. this data applied to the formula above for the subsequent reads assuming the data output hold time is one clock: 14 ns + 4 ns 20 ns data output will be available and valid at every clock period. consider the cpu frequency at 60 mhz, and fcc is 4. clock period is 16.6 ns. the initial access time is calculated to be 100 ns (4 latencies). this condition satisfies t avqv (ns) + t add (ns) + t data (ns) = 90 ns + 6 ns + 4 ns = 100 ns. however, the data output hold time of one clock violates burst data output zero wait-states: t chqv (ns) + t data (ns) one clk period 14 ns + 4 ns = 18 ns is not less than one clock period. to satisfy the formula above the data output hold time must be set a 2 clocks to correctly allow for data output setup time. this formula is also satisfied if the cpu has t data (ns) 2 ns, which yields: 14 ns + 2 ns 16.6 ns in page mode reads the initial access time can be determined by the formula: t add (ns) + t data (ns) + t avqv (ns) (5) and subsequent reads in page mode are defined by: t apa (ns) + t data (ns) (minimum time) (6) table 7. frequency configuration settings frequency configuration code input clk frequency C95 C120 v cc = 3.0 vC3.6 v v cc = 2.7 vC3.6 v v cc = 2.7 vC3.6 v 1 reserved reserved reserved 2 40 mhz 38 mhz 30 mhz 3 50 mhz 47 mhz 38 mhz 4 60 mhz 57 mhz 46 mhz 5 66 mhz 66 mhz 53 mhz 6 60 mhz
28f800f3 and 28f160f3 21 4.9.4 wait # configuration C (rcr.8) the wait# configuration bit controls the behavior of the wait# output signal. this output signal can be set to be asserted during or one clk cycle before an output delay when continuous burst length is enabled. its setting will depend on the system and cpu characteristic. 4.9.5 burst sequence C (rcr.7) the burst sequence specifies the order in which data is addressed in synchronous burst mode. this order is programmable as either linear or intel burst order. the continuous burst length only supports linear burst order. the order chosen will depend on the cpu characteristic. see table 8 for more details. figure 9. output configuration dq 15-0 (d/q) valid output dq 15-0 (d/q) valid output valid output valid output clk (c) 1 clk data hold 2 clk data hold table 8. sequence and burst length starting addr. (dec.) burst addressing sequence (dec.) 4-word burst length 8-word burst length continuous burst linear intel linear intel linear 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-... 3 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-.. 5 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-... 8 na 8-9-10-11-12-13-14-... 9 na ... 15 na 15-16-17-18-19-20-21-...
28f800f3 and 28f160f3 22 4.9.6 clock configuration C (rcr.6) the clock configuration configures the device to start a burst cycle, output data, and assert wait# on the rising or falling edge of the clock. clk flexibility helps ease 3 volt fast boot block flash memory interface to a wide range of burst cpus. 4.9.7 burst length C (rcr.20) the burst length is the number of words that the device will output. the device supports burst lengths of four and eight words. in four- or eight-word burst configuration the device will perform a wrap around type burst access (see table 8 ). it also supports a continuous burst mode. in continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the devices burstable address space. bits rcr.2C0 in the read configuration register set the burst length. 4.9.8 continuous burst length when operating in the continuous burst mode, the flash memory may incur an output delay when the burst sequence crosses the first 16-word boundary. the starting address dictates whether or not a delay will occur. if the starting address is aligned to a four-word boundary, the delay will not be seen. if the starting address is the end of a four-word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. the delay will only take place once during a continuous burst access, and if the burst sequence never crosses a 16-word boundary, the delay will never happen. using the wait# output pin in the continuous burst configuration, the system is informed if this output delay occurs.
28f800f3 and 28f160f3 23 figure 10. automated block erase flowchart suspend blk. erase loop start write 20h, block address write d0h, block address read status register sr.7 = full status check if desired block erase complete full status check procedure repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear staus register command, in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend block erase 1 0 comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pp error detect check sr.1 1 = device protect detect wp# = v il read status register data (see above) v pp range error device protect error block erase successful sr.3 = sr.1 = 1 0 1 0 command sequence error sr.4, 5 = 1 0 block erase error sr.5 = 1 0 status register data check sr.4, 5 both 1 = command sequence error check sr.5 1 = block erase error bus operation write write standby read command erase setup erase confirm bus operation standby standby standby standby command
28f800f3 and 28f160f3 24 figure 11. automated program flowchart suspend program loop start write 40h, address write data and address read status register sr.7 = full status check if desired program complete full status check procedure repeat for subsequent byte writes. sr full status check can be done after each byte write or after a sequence of program operations. write ffh after the last byte write operation to place device in read array mode. sr.4, sr.3 and sr.1 are only cleared by the clear staus register command, in cases where multiple locations are written before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend program 1 0 comments data = 40h addr = location to be written data = data to be written addr = location to be written check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pp error detect check sr.1 1 = device protect detect wp# = v il read status register data (see above) v pp range error device protect error program successful sr.3 = sr.1 = 1 0 1 0 program error sr.4 = 1 0 status register data check sr.4 1 = data write error bus operation write write standby read command program setup data bus operation standby standby standby command
28f800f3 and 28f160f3 25 figure 12. block erase suspend/resume flowchart start write b0h read status register comments data = b0h addr = x data = d0h addr = x sr.7 = sr.6 = block erase completed write ffh read array data 0 1 0 status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = block erase suspended 0 = block erase completed read or byte write? command erase suspend erase resume bus operation write write read standby standby yes program program loop done write d0h block erase resumed read read array data no 1 data = ffh addr = x read array or program write read array or program loop
28f800f3 and 28f160f3 26 figure 13. program suspend/resume flowchart start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 0 read array locations from block other than that being written status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation write write read read standby standby write command program suspend read array program resume
28f800f3 and 28f160f3 27 5.0 data protection the 3 volt fast boot block flash memory architecture features two hardware-lockable parameter blocks, so critical code can be kept secure while six other parameter blocks can be programmed or erased as necessary to facilitate eeprom emulation. 5.1 v pp v pplk for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. when v pp is below v pplk , any block erase or program operation will result in a error, prompting the corresponding status register bit (sr.3) to be set. 5.2 wp# = v il for block locking the lockable blocks are locked when wp# = v il ; any block erase or program operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two parameter blocks (blocks #37, #38 for the 16 mbit, blocks #21, #22 for the 8 mbit) are lockable. for the bottom configuration, the bottom two parameter blocks (blocks #0, #1) are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 5.3 wp# = v ih for block unlocking wp# controls all block locking and v pp provides protection against spurious writes. table 9 defines the write protection methods. table 9. write protection truth table v pp wp# rst# write protection provided xxv il all blocks locked v il xv ih all blocks locked 3 v pplk v il v ih lockable blocks locked 3 v pplk v ih v ih all blocks unlocked
28f800f3 and 28f160f3 28 6.0 v pp voltages intel 3 volt fast boot block flash memory provides in-system programming and erase at 2.7 vC 3.6 v (3.0 vC3.6 v for automotive temperature) v pp . for customers requiring fast programming in their manufacturing environment, this family of products includes an additional high-performance 12 v programming feature. the 12 v v pp mode enhances programming performance during short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during block erase and program operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 7.0 power consumption while in operation, the flash device consumes active power. however, intel ? flash devices have power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is idle. when ce# is not asserted, the flash enters its standby mode, where current consumption is even lower. the combination of these features minimizes overall memory power and system power consumption. 7.1 active power with ce# at a logic-low level and rst# at a logic-high level, the device is in active mode. active power is the largest contributor to overall system power consumption. minimizing active current has a profound effect on system power consumption, especially for battery-operated devices. 7.2 automatic power savings automatic power savings (aps) provides low-power operation during active mode, allowing the flash to put itself into a low current state when not being accessed. after data is read from the memory array, the devices power consumption enters the aps mode where typical i cc current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read. 7.3 standby power with ce# at a logic-high level (v ih ) and the cui in read mode, the flash memory is in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs (dq 0 Cdq 15 ) are placed in a high-impedance state independent of the status of the oe# signal. if ce# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
28f800f3 and 28f160f3 29 system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this will provide a more accurate measure of application-specific power and energy requirements. 7.4 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp , v cc , or v ccq , powers-up first. 7.4.1 rst# connection the use of rst# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rst# to the system reset signal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rst# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 7.4.2 v cc , v pp and rst# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode or after v cc transitions above v lko (lockout voltage), is read array mode. after any block erase or program operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. 7.5 power supply decoupling flash memorys power switching characteristics require careful device de-coupling. system designers should consider three supply current issues: ? standby current levels (i ccs ) ? active current levels (i ccr ) ? transient peaks produced by falling and rising edges of ce#.
28f800f3 and 28f160f3 30 transient current magnitudes depend on the device outputs capacitive and inductive loading. two- line control and proper de-coupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 7.5.1 v pp trace on printed circuit boards designing for in-system writes to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. v pp trace widths and layout should be similar to that of v cc . adequate v pp supply traces, and de-coupling capacitors placed adjacent to the component, will decrease spikes and overshoots. 8.0 electrical specifications 8.1 absolute maximum ratings notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc and v pp pins. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins is 5.5 v and v cc and v ccq is v cc + 0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. v pp program voltage is normally 2.7 vC3.6 v. connection to supply of 11.4 vC12.6 v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp may be connected to 12 v for a total of 80 hours maximum. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. parameter maximum rating temperature under bias C40 c to +125 c storage temperature C65 c to +125 c voltage on any pin (except v cc , v ccq , and v pp ) C0.5 v to +5.5 v (1) v pp voltage C0.5 v to +13.5 v (1, 2, 4) v cc and v ccq voltage C0.2 v to +5.0 v (1) output short circuit current 100 ma (3) notice: this datasheet contains information on products in full production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design .
28f800f3 and 28f160f3 31 8.2 extended temperature operating conditions note: 1. see dc characteristics tables for voltage range-specific specifications. 2. the voltage swing on the inputs, v in is required to match v ccq . 3. applying v pp = 11.4 vC12.6 v during a program or erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. a hard connection to v pp = 11.4 vC12.6 v is not allowed and can cause damage to the device. 4. v cc , v ccq , and v pp1 must share the same supply when all three are between 2.7 v and 3.6 v. 8.3 capacitance (1) t a = +25 c, f = 1 mhz note: 1. sampled, not 100% tested. symbol parameter notes min max unit t a operating temperature C40 +85 c v cc1 v cc supply voltage 1 2.7 2.85 v v cc2 v cc supply voltage 1 2.7 3.3 v v cc3 v cc supply voltage 1,4 2.7 3.6 v v ccq1 i/o voltage 1,2 1.65 2.5 v v ccq2 i/o voltage 1,2 1.8 2.5 v v ccq3 i/o voltage 1,2,4 2.7 3.6 v v ccq4 i/o voltage 1 4.75 5.25 v v pp1 v pp supply voltage 1 2.7 3.6 v v pp2 v pp supply voltage 1,4 11.4 12.6 v cycling block erase cycling 3 100,000 cycles symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v
28f800f3 and 28f160f3 32 8.4 dc characteristicsextended temperature (1) sym parameter v cc 2.7 vC3.6 v 2.7 vC2.85 v 2.7 vC3.3 v unit test conditions v ccq 2.7 vC3.6 v 1.65 vC2.5 v 1.8 vC2.5 v note typ max typ max typ max i li input load current 2 1 1 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 2 10 10 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd output leakage current for wait# 25 25 25 i ccs v cc standby current 3 30 75 20 75 150 250 a v cc = v cc max ce# = rst # = v cc i ccr v cc read current 3 456030454055ma asynchronous t avqv = min v in = v ih or v il ce# = v il oe# = v ih 45 60 30 45 40 55 ma synchronous clk = 33 mhz ce# = v il oe# = v ih burst length = 8 word i ccw v cc program current 3,4 8 20 8 20 8 20 ma v pp = v pp1 or v pp2 program in progress i cce v cc erase current 3,4 8 20 8 20 8 20 ma v pp = v pp1 or v pp2 erase in progress i ppr v pp read current 2 15 2 15 2 15 a v pp v cc 2,3 50 200 50 200 50 200 a v pp > v cc i ppw v pp program current 2,4,5103510351035ma v pp =v pp1 program in progress 210210210ma v pp = v pp2 program in progress i ppe v pp erase current 2,4,5122513251325ma v pp = v pp1 program in progress 825825825ma v pp = v pp2 program in progress i ppes i ppws v pp erase suspend current 2,3 50 200 50 200 50 200 a v pp = v pp1 or v pp2 program or erase suspend in progress i ccws i cces v cc program suspend or block erase suspend current 1,8 95 95 250 a v cc = v cc max ce# = rst# = v cc wp# = vcc or gnd
28f800f3 and 28f160f3 33 notes: 1. all currents are in rms unless otherwise noted. typical values at normal v cc , t a = +25 c. 2. applying v pp = 11.4 vC12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. 3. the specification is the sum of v cc and v ccq currents. 4. erases and program operations are inhibited when v pp v pplk , and not guaranteed outside the valid v pp ranges of v pp1 and v pp2 . 5. sampled, not 100% tested. 6. i cces is specified with device deselected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . 7. automatic power savings (aps) reduces i ccr to approximate standby levels, in static operation. 8. i ccws and i cces are specified with the evice disabled. if the device is read or written while in suspend mode, the devices current draw is i ccr or i ccw . dc characteristics, continued v cc 2.7 vC3.6 v 2.7 vC2.85 v 2.7 vC3.3 v sym parameter v ccq 2.7 vC3.6 v 1.65 vC2.5 v 1.8 vC2.5 v unit test conditions note min max min max min max v il input low voltage C0.4 0.22 * v cc C0.2 0.2 C0.2 0.2 v v ih input high voltage 2.0 5.5 v ccq C 0.2 v ccq + 0.2 v ccq C 0.2 v ccq + 0.2 v v ol output low voltage 0.10 -0.10 0.10 -0.10 0.10 v v cc = v cc min v ccq = v ccq min i ol = 100 m a v oh output high voltage v ccq C 0.1 v ccq C 0.1 v ccq C 0.1 v v cc = v cc min v ccq = v ccq min i oh = C100 m a v pplk v pp lock-out voltage 4 1.5 1.5 1.5 v complete write protection v pp1 v pp during program and erase operations 62.73.6 v v pp2 6 2.7 2.85 v v pp3 62.73.3v v pp4 6,7 11.4 12.6 11.4 12.6 11.4 12.6 v v lko v cc prog/erase lock voltage 1.5 1.5 1.5 v v lko2 v ccq prog/erase lock voltage 1.2 1.2 1.2 v
28f800f3 and 28f160f3 34 note: ac test inputs are driven at v ccq min. for a logic "1" and 0.0 v for a logic "0." input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v ccq = 2.7 v. note: see table for component values. note: c l includes jig capacitance. figure 14. ac input/output reference waveform for v cc = 2.7 v3. 6 v v ccq 0v v ccq /2 v ccq /2 t est p o in ts input output figure 15. ac equivalent testing load circuit device under test v ccq c l r 2 r 1 out test configuration c l (pf) r 1 ( w ) r 2 ( w ) 2.7 v standard test 50 25k 25k 1.65 v standard test 50 16.7k 16.7k
28f800f3 and 28f160f3 35 8.5 ac characteristicsread-only operations (1,2) extended temperature notes: 1. see figure 14, ac input/output reference waveform for vcc = 2.7 v3. 6 v on page 34 for timing measurements and maximum allowable input slew rate. 2. data bus voltage must be less than or equal to v ccq when a read operation is initiated to guarantee ac specifications. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 5. oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 6. adv# tied to ground, t ehel (ce# high pulse width) must be held high for a minimum of 15 ns. # symbol parameter product C95 C120 unit v cc 3.0 v 3.6 v 2.7 v 3.6 v 2.7 v 3.6 v notes min max min max min max r1 t clk clk period 15 15 15 ns r2 t ch (t cl ) clk high (low) time 2.5 2.5 2.5 ns r3 t chcl clk fall (rise) time 5 5 5 ns r4 t avch address valid setup to clk 7 7 7 ns r5 t vlch adv# low setup to clk 7 7 7 ns r6 t elch ce# low setup to clk 11 11 11 ns r7 t chqv clk to output delay 15 19 23 ns r8 t chqx output hold from clk 3 3 3 3 ns r9 t chax address hold from clk 4 10 10 10 ns r10 t chtl clk to wait# delay 14 16 23 ns r11 t avvh address setup to adv# high 10 10 10 ns r12 t elvh ce# low to adv# high 10 10 10 ns r13 t avqv address to output delay 90 95 120 ns r14 t elqv ce# low to output delay 5 90 95 120 ns r15 t vlqv adv# low to output delay 90 95 120 ns r16 t vlvh adv# pulse width low 10 10 10 ns r17 t vhvl adv# pulse width high 10 10 10 ns r18 t vhax address hold from adv# high 3 3 3 ns r19 t apa page address access time 25 27 35 ns r20 t glqv oe# low to output delay 25 25 30 ns r21 t phqv rst# high to output delay 600 600 600 ns r22 t ehqz t ghqz ce# or oe# high to output in high z, whichever occurs first 3151515ns r23 t oh output hold from address, ce#, or oe# change, whichever occurs first 3000ns r24 t ehel ce# high pulse width 6 0 0 0 ns
28f800f3 and 28f160f3 36 figure 16. ac waveform for clk input figure 17. ac waveform for single asynchronous read operations from parameter blocks, status register, identifier codes r1 r2 r3 clk (c) r18 a 19-0 (a) v ih v il valid address r11 r13 r20 r23 dq 15-0 (d/q) rst# (r) r21 v ih v il v oh v ol valid output high z oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r15 r16 adv# (v) v ih v il r17 r12 r14 r22 ce# (e) v ih v il
28f800f3 and 28f160f3 37 figure 18. ac waveform for asynchronous page mode read operations from main blocks r18 r11 r15 r13 r22 a 19-2 (a) a 1-0 (a) adv# (v) ce# (e) v ih v il v ih v il v ih v il v ih v il valid address valid address valid address valid address valid address r14 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r19 r23 dq 15-0 (d/q) rst# (r) r21 v ih v il v oh v ol valid out p ut valid out p ut valid out p ut valid out p ut hi g h z r17
28f800f3 and 28f160f3 38 notes: 1. 1.depending upon the frequency configuration code value in the read configuration register, insert clock cycles: frequency configuration 2 insert two clock cycles frequency configuration 3 insert three clock cycles frequency configuration 4 insert four clock cycles frequency configuration 5 insert five clock cycles frequency configuration 6 insert six clock cycles see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 19. ac waveform for single synchronous read operations from parameter blocks, status register, identifier codes v ih v il clk [c] a 19-0 [a] v ih v il r4 r12 r18 r11 r16 r22 adv# [v] ce# [e] v ih v il v ih v il r6 r5 oe# [g] we# [w] v ih v il v ih v il wait# [t] v oh v ol r20 r7 r23 dq 15-0 [d/q] v oh v ol r9 r13 r15 r14 r8 valid address high z valid output r17 note 1
28f800f3 and 28f160f3 39 notes: 1. 1.depending upon the frequency configuration code value in the read configuration register, insert clock cycles: frequency configuration 2 insert two clock cycles frequency configuration 3 insert three clock cycles frequency configuration 4 insert four clock cycles frequency configuration 5 insert five clock cycles frequency configuration 6 insert six clock cycles see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 20. ac waveform for synchronous burst read operations, four-word burst length, from main blocks v ih v il clk (c) note 1 a 19-0 (a) v ih v il valid address r4 r18 r11 r9 r12 r16 r22 adv# (v) ce# (e) v ih v il v ih v il r6 r5 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r7 r8 r23 dq 15-0 (d/q) v oh v ol valid output valid output valid output valid output high z r17
28f800f3 and 28f160f3 40 notes: 1. this delay will only occur when burst length is configured as continuous. see section 4.9.7 for further information about burst length configuration. 2. wait# is configurable. it can be set to assert during or one clk cycle before an output delay. see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. notes: 1. this delay will only occur when burst length is configured as continuous. see section 4.9.7 for further information about burst length configuration. 2. wait# is configurable. it can be set to assert during or two clk cycles before an output delay. see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 21. ac waveform for continuous burst read, showing an output delay with data output configuration set to one clock v ih v il clk (c) note 1 a 19-0 (a) adv# (v) ce# (e) oe# (g) we# (w) v ih v il v ih v il v ih v il v ih v il v ih v il wait# (t) v oh v ol dq 15-0 (d/q) v oh v ol valid output valid output valid output high z valid output valid output r7 r10 r10 note 2 figure 22. ac waveform for continuous burst read, showing an output delay with data output configuration set to two clocks v ih v il clk (c) note 1 a 19-0 (a) adv# (v) ce# (e) oe# (g) we# (w) v ih v il v ih v il v ih v il v ih v il v ih v il wait# (t) v oh v ol dq 15-0 (d/q) v oh v ol valid output high z valid output r7 r10 note 2 r10
28f800f3 and 28f160f3 41 8.6 ac characteristicswrite operations (1, 2) extended temperature notes: 1. see figure 14, ac input/output reference waveform for vcc = 2.7 v3. 6 v on page 34 for timing measurements and maximum allowable input slew rate. 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . 5. refer to table 3 for valid a in and d in for block erase or program. 6. write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph = t whwl = t ehel = t whel = t ehwl . 7. t whgl is 15 ns unless resuming a program suspend or erase suspend command; then 30 ns is required before read can be commenced. 8. v pp should be held at v pph1 or v pph2 until determination of block erase or program success. # sym parameter valid for all speed and voltage combinations unit notes min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) going low 3 600 ns w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 4 0 ns w3 t wp (t wlwh ) write pulse width 4 75 ns w4 t vlvh adv# pulse width 10 ns w5 t dvwh (t dveh ) data setup to we# (ce#) going high 5 70 ns w6 t avwh (t aveh ) address setup to we# (ce#) going high 5 75 ns w7 t vleh (t vlwh ) adv# setup to we# (ce#) going high 75 ns w8 t avvh address setup to adv# going high 10 ns w9 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns w10 t whdx (t ehdx ) data hold from we# (ce#) high 0 ns w11 t whax (t ehax ) address hold from we# (ce#) high 0 ns w12 t vhax address hold from adv# going high 3 ns w13 t wph (t whwl ) write pulse width high 6 20 ns w14 t bhwh (t bheh ) wp# setup to we# (ce#) going high 3 200 ns w15 t vpwh (t vpeh )v pp setup to we# (ce#) going high 3 200 ns w16 t whgl (t ehgl ) write recovery before read 7 15 ns w17 t qvbl wp# hold from valid srd 3,8 0 ns w18 t qvvl v pp hold from valid srd 3,8 0 ns
28f800f3 and 28f160f3 42 notes: 1. v cc power-up and standby. 2. write block erase or program setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operations, oe# and ce# must be driven active, and we# de-asserted. figure 23. ac waveform for write operations valid address valid address w6 w11 w12 w3 w5 w10 w9 w2 w1 w13 data in data in valid srd w4 w7 w8 w16 a 20-0 (a) v ih v il adv# (v) v ih v il ce# (we#) [e(w)] v ih v il oe# [g] v ih v il we# (ce#) [w(e)] v ih v il data [d/q] v ih v il note 6 note 6 note 1 note 2 note 3 note 4 note 5 rst# [p] v ih v il w15 w18 v pp [v] v pph1/2 v pplk v il wp# [b] v ih v il w14 w17 w19
28f800f3 and 28f160f3 43 8.7 ac characteristicsreset operationextended temperature notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if t plph is < 100 ns the device may still reset but this is not guaranteed. 3. sampled, but not 100% tested. 4. if rst# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. figure 24. ac waveform for reset operation table 10. reset specifications (1) number symbol parameter notes min max unit p1 t plph rst# low to reset during read (if rst# is tied to v cc , this specification is not applicable) 2,3 100 ns p2 t plrh rst# low to reset during block erase or program 3,4 22 s (a) reset while device is in read mode rst# (r) v ih v il p1 r20 rst# (r) v ih v il p1 p2 r20 rst# (r) v ih v il p1 p2 r20 (b) reset during program or block erase, p1 p2 (c) reset during program or block erase, p1 3 p2 abort complete abort complete
28f800f3 and 28f160f3 44 8.8 extended temperature block erase and program performance (1,2,3) notes: 1. these performance numbers are valid for all speed versions. 2. sampled, but not 100% tested. 3. reference the figure 23, ac waveform for write operations on page 42 . 4. typical values measured at t a = +25 c and nominal voltages. subject to change based on device characterization. 5. excludes system-level overhead. # sym parameter notes 2.7 v-3.6 v v pp 11.4 v-12.6 v v pp unit typ (4) max typ (4) max w19 t whrh1 , t ehrh1 program time 5 23.5 200 8 185 s block program time (parameter) 5 0.10 0.30 0.03 0.10 sec block program time (main) 5 0.8 2.4 0.24 0.8 sec t whrh2 , t ehrh2 block erase time (parameter) 5 1 4 0.8 4 sec block erase time (main) 5 1.8 5 1.1 5 sec t whrh5 , t ehrh5 program suspend latency 6 10 5 10 s t whrh6 , t ehrh6 erase suspend time 13 20 10 12 s
28f800f3 and 28f160f3 45 9.0 ordering information note: 1. the 56-ball bga package topside mark reads f160f3. all product shipping boxes or trays provide the correct information regarding bus architecture. valid combinations 56-lead ssop 56-lead tsop 8 x 8 easy bga 56-ball bga csp (1) extended 16 m dt28f160f3t120 te28f160f3t120 rc28f160f3t120 gt28f160f3t120 dt28f160f3b120 te28f160f3b120 rc28f160f3b120 gt28f160f3b120 dt28f160f3t95 te28f160f3t95 RC28F160F3T95 gt28f160f3t95 dt28f160f3b95 te28f800f3b95 rc28f800f3b95 gt28f800f3b95 extended 8 m dt28f800f3t120 te28f800f3t120 rc28f800f3t120 dt28f800f3b120 te28f800f3b120 rc28f800f3b120 dt28f800f3t95 te28f800f3t95 rc28f800f3t95 dt28f800f3b95 te28f800f3b95 rc28f800f3b95 d t 2 8 f 1 6 0 f 3 t 1 2 0 package dt = extended temp., 56-lead ssop gt = extended temp., 56-ball bga* csp te = extended temp., 56-lead tsop rc = extended temp., easy bga product line designator for all intel ? flash products access speed (ns) (120,150) product family f3 = 3 volt fast boot block v cc = 2.7 v - 3.6 v v pp = 2.7 v - 3.6 v or 11.4 v - 12.6 v device density 160 = x16 (16-mbit) 800 = x16 (8-mbit) t = top blocking b = bottom blocking
28f800f3 and 28f160f3 46 10.0 additional information notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. visit intels world wide web home page at http://www.intel.com or http://developer.intel.com for technical documentation and tools. order number document/tool 297939 3 volt fast boot block flash memory specification update 210830 flash memory databoo k 292213 ap-655 3 volt fast boot block design guide 298161 intel ? flash memory chip scale package users guide contact your intel representative intel ? flash data integrator (ifdi) software developers kit 297874 ifdi interactive: play with intel ? flash data integrator on your pc

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